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Intelligent Signal Gating-Aware Energy-Efficient 8-Bit FinFET Arithmetic and Logic Unit

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Abstract

A FinFET-based 8-bit low-power arithmetic and logic unit (ALU) with full-swing 9-transistor GDI-hybrid full adder has been presented in this research paper. An intelligent signal gating-aware energy-efficient ALU is proposed using this adder and signal gating circuit. An adaptive signal gating is applied according to the current ALU operation based on the particular operation corresponding control word. The input signals to the other blocks are gated such that the proposed intelligent signal gating scheme customizes the overall power utilization of the proposed ALU. The proposed ALU has been implemented using 20 nm FinFET PTM models. The total power consumption of the conventional FinFET ALU to execute all eight operations is 619.55 µW, whereas the proposed ALU consumes 225.53 µW only. The average power consumption of the traditional FinFET ALU is 77.44 µW per operation, while the proposed low-power ALU needs 28.19 µW only. The maximum amount of total and average power that the proposed scheme can optimize is 63.59%.

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The details of all the data generated and analysed during this work are included in this article.

Abbreviations

Vdd:

Supply voltage

V :

Volts

µ :

Micro

G :

Giga

nm :

Nanometer

FET:

Field-effect transistor

FinFET:

Fin Field Effect Transistor

PTM:

Predictive Technology Model

MOSFET:

Metal-Oxide-Semiconductor FET

SCE:

Short-channel effects

SG:

Short-gate

LP:

Low-power

IG:

Independent-gate

ALU:

Arithmetic and logic unit

GDI:

Gate-diffusion input

CNTFET:

Carbon nanotube FET

SOI:

Silicon on insulator

ADE:

Analog Design Environment

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Ajitha, D., Chandra Sekhar Reddy, M. Intelligent Signal Gating-Aware Energy-Efficient 8-Bit FinFET Arithmetic and Logic Unit. Circuits Syst Signal Process 41, 299–320 (2022). https://doi.org/10.1007/s00034-021-01775-w

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